Q: What is the difference between a flip-flop and a latch?
A:
_______ _______
D | | Q D | | Q
-----| |---- -----| |----
clock | | enable | |
-----> | _ -----| | _
| | Q | | Q
| |---- | |----
|_______| |_______|
The example shows D-latch and D-FF.
The simplest form of data storage is latch.
It's output responds immediately
to changes at the input and the input state will be
remembered, or "latched" onto.
While "enable" input is active the input of the latch is transparent
to the output, once "enable" is deactivated the output remains locked.
Flip-flops use clock as a control input.
The transition on output Q occurs only at the edge
of the clock pulse. Input data must present T_setup time before the
clock edge and remain T_hold time after.
* RESET input, while it is not shown, is present in most FF.
module DFF (Q,_Q,D,clk,rst);
output Q,_Q;
input D,clk,rst;
reg Q,_Q;
always @(posedge clk or posedge rst)
begin
if (rst) Q <= 0;
else Q <= D;
_Q <= !Q;
end
endmodule
module DLatch (Q,_Q,D,en,rst);
output Q,_Q;
input D,en,rst;
reg Q,_Q;
always @(en or D or posedge rst)
begin
if (rst) Q <= 0;
else if (en) Q <= D;
_Q <= !Q;
end
endmodule
