_______________________
| |
| |
| |\ |
| | \ |
|_______| \ |
| o \ |
| | | out
in | |___________|_______
_______________| 1 |
| /
| /
| /|
|/ |
clock |
__________________|
This is a D-latch implemented from 2-input mux. It works this way:
At every clock =1 out=in,
when clock =0 out= last in
