The picture below illustrates general computer structure. There are three subsystems: CPU, Memory, IO ports(periferal devices).
Basic CPU operations:
- fetching the instruction from memory,
- decode the instruction,
- execute command and write the result data back to the memory or to I/O device.
Here is an example of timing diagram. Every bus cycle in this example consists of 4 clock periods. All operations are
synchronous with the clock.
To write into memory CPU sets the address,during the next clock cycle - DATA. Then CPU activates control signal MEM_WR
(active low) and
on the rising edge of MEM_WR the DATA is latched into the memory device. In this example (applicable to all x86 systems)
memory and IO devices have different address space. To exchange data with IO port CPU activates IO_WR or IO_RD signals.
The table below illustrates Intel x86 CPU family
||L1 32K,L2 512K
|Floating point unit
First steps after powering up.
After Powering Up Reset signal is activated and CPU starts fetching and execute instructions.
The first instruction is always located 16 locations below the very top of the memory address space FFFFFF0h
(all x86 based computers).This location belongs to BIOS ROM.
BIOS contains software, that provides memory test,initialization of peripheral devices,creates interrupt vector table,
boots operation system.
Later on this information can be overridden when PLAG-and-PLAY software starts working.
This is a modern Pentium III based computer .
CPU bus has a clock speed 100 - 133 MHz. Memory and IO devices can't work at this speed.
In order to separate slower devices and relieve the CPU there are North and South
bridges. They are named according to their location to the PCI bus (to the north of PCI and to the south).
North bridge dispatches CPU commands to SDRAM , cashe (level2), IO devices through PCI bus
and video through AGP interface (abbreviation of AGP is Accelerated Graphics Port).
Once CPU sets the address and control lines to define what type
of transaction it wants like WR or RD, North bridge knows where to forward the command and reports back to
CPU when it is done.
South bridge contains USB,IDE controllers and ISA interface.
IDE is an interface to CDROM and hard drives.
ISA devices are kept for compatibility with older computers. Parallel , serial port devices
work through slow (8 MHz) ISA bus. BIOS ROM is connected to ISA bus too.
PCI bus was developed by Intel for high performance peripheral devices,
such as graphic accelerators, disk controllers, data acquisition boards.
PCI was supposed to overcome limitations of existing ISA bus .
16 bit ISA bus with clock speed of 10 MHz with theoretical bus throughput 2M transfers/sec
but practically not more than 500k.
PCI bus is much faster:
in burst mode PCI can transfer 32 or 64 bit data with 33 MHz or 64 MHz clock, that yields
transfer rates from 132 MB/sec to 538 MB/sec
PCI supports huge address range: 32/64 bit address bus instead of 16 bit ISA
It is a burst oriented bus designed for large transfers; hidden bus arbitration
among multiple musters is provided on each bus.
In theory upto 32 logical devices can reside on PCI bus. But practically,a PCI bus is more likely
to have maximum 10 devices because of it's low-powered, reflected wave-swithching .
If more devices is desired PCI to PCI bridge is used.
PCI devices are automatically configured in software (Plug and Play option).
This eliminates earlier problems with ISA configuration using fixed addresses or user
configured switches and jumpers.
In recent years some peripheral devices have gotten faster and PCI became too slow
for CD and hard disks. Then new interfaces appeared : IDE,SCSI.
AGP port.When 3D graphics applications became common, graphic devices were still found on the PCI bus.
AGP port provides high speed access to the memory and allows to share it with local video memory.
AGP is not a bus ( no competition between devices sitting on the same bus), but port with
a dedicated connection between North bridge and graphic accelerator. Speed is 264 MB/s - 1 GB/s.
ISA bus first appeared in PC based on 80286 CPU.
The idea was to put a standard in interfacing with peripheral devices.In our days this bus is kept for compatibility with "legacy" peripheral devices
such as BIOS ROM,Parallel and Serial Ports,Sound and Modem devices.
These devices have historical fixed address range (no Plug and Play option) and aren't hurt by low
speed of ISA bus (8/16 bit data bus with 8 MHz clock speed).
Most modern PCs don't even have extra ISA slots since most peripheral components moved to PCI and USB.
ISA bus requires 4 bus cycles for each data transfer .
USB bus has lots of advantages in comparison with ISA and PCI bus:
For more information on USB click here.
- Add-in slots are limited on internal PC buses while USB allows up to 127 devices.
- Add-ins require opening PC, inviting new problems while USB has standard external connector.
- External peripheral connectors (printer,keyboard,mouse,etc.) vary, while USB has one type of connection.
- USB connector has just 4 signals - cost saving on board design and cables. For example parallel port uses 25 pins connector.
- Peripheral interrupts are limited - sharing required. USB is using polling mechanizm instead.
- USB has power line. Peripherals can be powered directly from USB cable in the range of 100 - 500mA.
- USB supports hot auto configuration while PCI devices can only get identified during boot time.
- USB supports data rates upto 12Mb/s, new standard is going to extend it to 480 Mb/s.
A major competitor to USB in video streaming applications is a Fire Wire interface.
Fire Wire(IEEE 1394 standard bus) was developed by Apple for audio and video transfers.
It supports a rate upto 400 Mbps. However, if USB comes free with computer, you have to buy and add Fire Wire card as you need it.
serial port: 115kbits/s
standard parallel port: 115kBYTES/s
USB: 12Mbits/s (1.5MBYTES/s)
ECP/EPP parallel port: 3MBYTES/s
SCSI-2 (Fast SCSI, Fast Narrow SCSI): 10MBYTES/s
Fast Wide SCSI (Wide SCSI): 20MBYTES/s
Ultra SCSI (SCSI-3, Fast-20, Ultra Narrow): 20MBYTES/s
Wide Ultra SCSI: 40MBYTES/s
Ultra2 SCSI: 40MBYTES/s
IEEE-1394: 100-400Mbits/s (12.5--50MBYTES/s)
Wide Ultra2 SCSI: 80MBYTES/s
Ultra3 SCSI: 80MBYTES/s
Wide Ultra3 SCSI: 160MBYTES/s
FC-AL Fiber Channel: 100-400MBYTES/s
Pentium IV with PCI Express
The diagram below illustrates Pentium IV system. You can see that ISA bus is gone
and a new interface introduced: PCI Express. LPC is a subset of PCI (low pin count).
PCI Express provides
advanced features such as better power management, performance and bandwith increases, enables support for
streaming media, TV tuners, cameras, graphics.
PCI Express will obviously replace the Advanced Graphics Port (AGP) for connecting the processor to the graphics
chip. It will later replace the PCI bridge to provide a fast connection to peripherals such as cameras.
PCI Express has a maximum bandwidth of 8 gigabytes per second. AGP 8X tops out at 2.1 gigabytes per second,
and the PCI used in desktops generally peaks at 266 megabytes.
More information about PCI Express is available at
- PC Platform Mindshare class (Jan 2001)
- Understanding PCI-Bus subtleties optimizes system performance, Paul Schreier,EE Feb 2000
- Quenching processor thirst , Patrick Gelsinger, Electronics World, May 2001
- USB architecture, http://www.usb.org
- PCI SIG web site http://www.pcisig.org
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