Apr 2003
VLSI Basics
Alex Paikin , National Semiconductor , Apr 2003


MOS transistor

Voltage on gate controls current that flows between source and drain.
Vt - is the threshold voltage on the gate when drain current begins to flow.
To make the channel conductive Vgs has to be greater than Vt. To make the current flow Vdrain has to be greater than Vsource.

Here is how transistor looks on layout. Drain and source are usually of green or yellow color, gate is red. Transistor is formed when poly (red color) crosses diffusion layer.

W and L are geometry parameters,that actually define the technology. L - defines MAX current, because the larger L the lower R (electrical impedance).
From the other side, large W - means large Capacitance (C=EWL/d).
Capacitance is also increasing with higher integration .

VLSI Technology

PMOS technology based on p-MOS transistors was invented first.
NMOS technology based on n-MOS transistors was used later. n-MOS transistors have better conductance, smaller size and better speed/square performance.
CMOS technology combines n-MOS and p-MOS and has greatest power consumption parameters.
This image illustrates a cross section of CMOS inverter.

VLSI Fabrication

A typical submicron CMOS process uses p-type wafers. A blank 8-inch wafer costs about $100. An IC fabrication process contains a series of masking steps to create layers that define the transistors and metal interconnect. Most layers are formed by the following steps: put layer, protect needed area with photoresist, apply light to transpose, remove photoresist and unprotected layer areas. This photolithografy process is illustrated on the image:

n-well and p-well are formed by ion implantation, when ions of dopped silicon n+ or p+ are forced into wafer area with a great speed. During the implantation the ions can get inside to a depth of a few microns. Further transistor layers are formed by diffusion (high T ion migration). Gates are created from poly (polycristalline silicon). Poly has to have a good conductance. To improve the coductance poly is covered with a silicide (a metallic compaund of silicon). SIO2 is an insulator, it also protects the outer layer from oxidation. Layers of poly and SiO2 can be deposited using chemical vapor deposition (CVD). Metal layers can be deposited using sputtering.All these layers are patterned using masks and photolithografy process.

Power Consumtion

Static power consumption is defined by leakage. Leakage is a junction currents caused by thermally generated carriers. Their value increases exponentially with increasing junction T. For example, 85C (a common junction T) results in increase by a factor of 60 over room T.
Dynamic power consumption depends on a capacitive load:
W= CV2 (charging C to Vdd draws CV2 energy from power supply).
This energy is consumed for every 1 -> 0 and 0 -> 1 transition. Therefor, the higher clock frequency the higher power consumption (~f).
The alternative - is to lower V (power supply voltage).

1.Ravi Shanhar, VLSI and computer architecture
2.Norman G.Einspruch, VLSI Handbook
3.Erez Kleinman, Silicon process technology 3 day class handout, 1999
4.WEB references: www.intel.com, www.iue.tuwien.ac.at, www.computer.org

Apr 2003