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Hint from Hitequest: the FIFO should be 32words deep. James: In the hint, it says that the FIFO should be 32 word deep, but I don't understand that answer. First of all, the input is only 80 bits long. Why would we need a 32 word deep FIFO? The way I see it is since we have 100 write cycles to write that 80 bits, it also means that we have 1us (100 write cycle * 10ns per write cycle). In 1us, we can read 80 bits (1us * read cycle per 12.5ns). Thus, it seems to me that this system does not need any FIFO to write those 80 bits. Roni R: At worst case scenario all 80 words are in one burst. every 5 words that we write to the fifo we can read only 4. one is left.so after 80 words that we write we read only 64 => we need 16 words fifo to overcome diff between read & write clocks. Pete: The worst case scenario occurs when a burst beginning with 20 empty transfers is followed by a burst ending with 20 empty transfers. When this happens there is a continuous 100 MHz data stream of 160 transfers of which only 128 can be read out at 80 MHz. The FIFO needs to store the remaining 32 transfers. 100 MHz = 10 nS 80 MHz = 12.5 nS 10 nS x 160 = 1600 nS to write the data 1600 nS / 12.5 nS = 128 reads performed during the write 160 writes - 128 reads = 32 unread transfers that must be held |
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