We have a FIFO which clocks data in at 100mhz and clocks data out at 80mhz. On the input there are only 80 data bits in any order during each 100 clocks.
In other words, a 100 input clock will carry only 80 data bits, and the other twenty clocks carry no data (data is scattered in any order).
How big the FIFO needs to be to avoid data over/under-run?
Hint from Hitequest:
the FIFO should be 32words deep.
In the hint, it says that the FIFO should be
32 word deep, but I don't understand that answer. First of
all, the input is only 80 bits long. Why would we need a
32 word deep FIFO?
The way I see it is since we have 100 write cycles to write
that 80 bits, it also means that we have 1us (100 write
cycle * 10ns per write cycle). In 1us, we can read 80 bits
(1us * read cycle per 12.5ns). Thus, it seems to me that
this system does not need any FIFO to write those 80 bits.
At worst case scenario all 80 words are in one burst.
every 5 words that we write to the fifo we can read only 4.
one is left.so after 80 words that we write we read only 64 =>
we need 16 words fifo to overcome diff between read & write