Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with different clocks. On the rising edge of clk the FIFO stores data and increments wptr. On the rising edge of clkb the data is put on the b-output,the rptr points to the next data to be read.
If the FIFO is empty, the b-output data is not valid. When the FIFO is full the existing data should not be overriden.
When rst_N is asserted, the FIFO pointers are asynchronously reset.