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# =Electronics Hardware Questions=

Q:
Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with different clocks. On the rising edge of clk the FIFO stores data and increments wptr. On the rising edge of clkb the data is put on the b-output,the rptr points to the next data to be read. If the FIFO is empty, the b-output data is not valid. When the FIFO is full the existing data should not be overriden. When rst_N is asserted, the FIFO pointers are asynchronously reset.

A:
module fifo1 (full,empty,clk,clkb,ain,bout,rst_N)
output [7:0] bout;
input [7:0] ain;
input clk,clkb,rst_N;
output empty, full;
reg [3:0] wptr, rptr;
...

endmodule

wptr --
 0 1 2 3 4 5 6 7 8 9 10 11 12
-- rptr

Multiple clocks add complexity to this design. We need to define conditions for Empty and Full signals, take care of WR and RD pointers.
Here is one of possible solutions.

Empty and Full flags:
assign empty=((wptr == rptr) && (w_flag == r_flag);
assign full=((wptr == rptr) && (w_flag == ~r_flag);

where w_flag is set when wptr =12 (end of FIFO). After that wptr is reset to 0. The same applies to r_flag and rptr.

Pointer handling:
if (wptr == 12) {w_flag,wptr} <= {~w_flag,4'b0000};
else wptr <= wptr+1;
if (rptr == 12) {r_flag,rptr} <= {~r_flag,4'b0000};
else rptr <= rptr+1;