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=Electronics Hardware Questions=

     
   

 
 
Q: Convert D-latch into divider by 2. What is the max clock frequency the circuit can handle ?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS
 
 
 
 
 
 
A: Anup
 
 

    _____________________
   |	 _______         |
   |	|	|   Q    |
   `----|D	|----    |
  clock |	|        |
   ----->	|   _	 | 		
   	|	|   Q    |
   	|	|--------'
	|_______|
	
	


	    ___     ___     ___
	   |   |   |   |   |   |
clock	___|   |___|   |___|   |___
	      _______
	     |	     |
Q	 ____|	     |___

	 ____	      ___
_	     |	     |
Q	     |_______| 


Any system with clock should meet setup and hold time conditions.
Besides, since there is a feedback from !Q to D, we should take 
care of D input timing: the data on D input should not change 
while the clock is high!
Otherwise the results are unpredictable.
To meet these conditions:

         t_clock_high <= T_prop
        
         t_clock_low  >= T_setup
         
         T_hold <= T_prop
                 
For example, if we take t_clock_high= t_clock_low = 6nS
Then clock period = 12nS, i.e max Freq = 80MHz