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Q: Flip flops
a)The simplest form of FF is Set-Reset FF.See the drawing and gate level schematic below.
.----.
_______ +------\ \
S | | Q o--------+
-----| |---- ,--+------/ / |
| | | -----' |
| | _ | NOR |
R | | Q | ______________________|
-----| |---- | |
|_______| |__|_____________________
| |
| .----. |
_ +------\ \ |
S R Q Q Comment o--------+
---------------------------------------- +------/ /
0 0 Q !Q Hold condition -----'
1 0 1 0 NOR
0 1 0 1
1 1 x x Not used
b)Gated RS FF
It has two more NAND gates on R and S lines.
_______
S | | Q
-----| |----
enable | |
-----| | _
R | | Q
-----| |----
|_______|
A signal gate_enable =1 enables the work of RS FF,and gate_enable =0 disables it.
c) D-latch
Gated RS FF can be transformed into D latch by addition of an inverter.
_______
D | | Q
___________|S |----
enabl__|________| |
__|__ | | _
\ / | | Q
\ / ___|R |----
v | |_______|
o |
|____|
When gate_enable=1 D latch is transparent (Q=D),
and when gate_enable =0 the data at the output remains latched.
d) Master-Slave FF
_______ _______
| | | |
____|D Q1|_______________|S Q2|---
| | | |
| | | |
| |_______________|R |
| c | | c |
|_______| |_______|
clock | |
___________|_______________o_________|
It contains 2 FF(D-latch and RS) and inverter and works this way:
When the clock = HIGH, Q1=D ; FF2 does not change it's state since it waits for a negative
clock polarity.
On the falling edge of clock master FF1 transfers it's state to the slave FF2.
e)Edge-triggered FF
_______
D | | Q
-----| |----
clock | |
-----> | _
| | Q
| |----
|_______|
_______
D | | Q
-----| |----
clock | |
----o> | _
| | Q
| |----
|_______|
Unlikely to the D-latch these FF are edge triggered. First works on the positive
edge and second on negative edge. Input data must present T_setup time before
clock edge and remain T_hold time after.
f) JK FF
_______
J | | Q
-----| |----
clock | |
-----> | _
K | | Q
-----| |----
|_______|
J K Q Comment
----------------------------------
0 0 Q-1 Hold previous state
1 0 1
0 1 0
1 1 !(Q-1) when J=K=1 the output will change its state every clock pulse
Every transaction takes place when the clock is active (level or edge).Usually JK FF
are edge triggered.JK FF can be easily transformed into D FF by setting invertor between J and K
_______
D | | Q
___________|J |----
| | |
clk --|--------> |
__|__ | | _
\ / | | Q
\ / ___|K |----
v | |_______|
o |
|____|
|
| | |
