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=Electronics Hardware Questions=
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Two capacitors are connected in parallel through a switch. C1= 1uF, C2=
0.25uF.
Initially the switch is open, C1 is charged to 10V. What happens if
we close the switch? No losses in wires and capacitors.
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There are 2 switches that control the light in the long corridor. Each one can turn the light on and off. How would you do the wiring circuit?
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What will be the voltage level between the two capacitors? The Vcc = 10v DC.
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Suppose, you work on a specification for a system with some digital parameters.
Usually a spec table has Min,Typ and Max colomns for each parameter. In which column would you put
a Setup time and a Hold time?
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Design a simple circuit based on combinational logic to double the
output frequency.
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8bit ADC with parallel output converts an input signal into digital numbers. You have
to come up with an idea of a circuit , that finds the MAX of every
10 numbers at the output of the ADC.
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For an 8-bit flash A/D converter with an input range from 0V to 2.55V, describe what happens when the input voltage
changes from 1.27V to 1.28V
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Our system has CPU, ALU and two 8bit registers but no memory. How to exchange the data inside registers ?
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We swapped 2 transistors in CMOS inverter (put n-transistor at the top and p-transistor
at the bottom).
Can this circuit work as a non-inverting buffer?
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To enter the office people have to pass through a hallway. Once someone
gets into the office the light turns on. The light turns off when noone is present in the
room. There are two registration sensors in the hallway. Build a state
machine diagram and design a circuit to control the light.
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Draw a CMOS inverter. Why does CMOS technology dominate in VLSI manufacturing?
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Design a FIFO 1 byte wide and 13 words deep. The FIFO is interfacing 2 blocks with different clocks.
On the rising edge of clk the FIFO stores data and increments wptr.
On the rising edge of clkb the data is put on the b-output,the rptr
points to the next data to be read.
If the FIFO is empty, the b-output data is not valid. When the FIFO is full the existing data should not be
overriden.
When rst_N is asserted, the FIFO pointers are asynchronously reset.
module fifo1 (full,empty,clk,clkb,ain,bout,rst_N)
output [7:0] bout;
input [7:0] ain;
input clk,clkb,rst_N;
output empty, full;
reg [3:0] wptr, rptr;
...
endmodule
Hint from Hitequest
- We have a circular wheel with half painted black and the other half
painted white. There are 2 censors mounted 45 degree apart at the
surface of this wheel( not touching the wheel) which give a "1" for
black and "0" for white passing under them. Design a circuit to detect
which way the wheel is moving. Can not assume any fixed position for
start.
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You have a circuit operating at 20 MHz and 5 volt supply. What are the options to reduce the power
consumption of the circuit - change operating frequency or the power supply voltage or else?
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What is the purpose of a diode next to relay on schematics?
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Describe a finite state machine that will detect three consecutive coin tosses (of one coin) that result in heads.
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How many bit combinations are there in a byte?
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More questions and answers here...
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